The present invention relates to semiconductor test devices which may use leakage current and compensation systems of leakage current.
Forming an MOS transistor, which may include a micro channel length, on a wafer may be difficult, more specifically, controlling the channel length of MOS transistor may be difficult. Techniques for controlling the micro channel length (e.g., a light source of shorter wavelength, a phase shift mask (PSM), a phase edge shift mask (PEMS) and an optical correct (OPC), etc.) may result in MOS transistors which may have a channel length greater than a critical channel length and may result in the malfunctioning of a semiconductor chip.
Each of the transistors and/or simple circuits (e.g., an inverter delay and/or a ring oscillator) may be formed on a wafer simultaneously, and may test MOS transistors. Parameters, which may indicate characteristics of transistors, may be extracted from the transistors and/or simple circuits, however, determining the parameters may become more difficult and may take a longer time because the semiconductor fabrication process, which may change the characteristic of MOS transistor, may become more complex. A leakage current may vary with the channel length in an off-mode of the MOS transistor, such that the leakage current may cause malfunctions of semiconductor chips which may be integrated with MOS transistors.
A thickness of oxide layer or layers in the MOS transistor may become smaller and the control of the MOS transistor may become more difficult by simplifying the semiconductor fabrication method. The leakage current may be increased by tunneling through the micro oxide layer and may cause the malfunctioning of the semiconductor circuits.
MOS capacitors, which may have a larger gate area, may be used at both terminals of a power supply source, and the gate leakage current may cause an electrical leakage. The leakage current may reduce a capacitance of the MOS capacitor and the circuit, which may include the capacitor, may operate abnormally.